1. Field of Invention
The present invention relates to an apparatus for digital signal processing, and more specifically, to a real time two-dimensional discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) circuit suitable for implementing in a very large scale integrated (VLSI) circuit.
2. Description of Related Art
Techniques for data compression have played an important role in an image-processing system due to increasingly large amounts of video data to be processed. Among all techniques for data compression, data coding or transformation is the most difficult part. The difficulties result from, in general, the complexity of implementing the coding or transform algorithm in a circuit as well as the inefficiency of the circuit. Since the DCT/IDCT process utilizes orthogonal transform techniques which have higher transformation efficiency, it has been widely used in video systems for data coding. Therefore, in order to satisfy requirements of some international video standards, such as Joint Picture Expert Group (JPEG), Motion Photography Expert Group (MPEG) and H.261, a fast real-time 2-D DCT/IDCT circuit is a great need.
In order to have input/output data maintained in continuity, a 2-D DCT/IDCT circuit can be formed by connecting two 1-D DCT/IDCT processors in series. Or in order to attain a higher transform efficiency, a 2-D transform algorithm may be directly implemented in a circuit. The latter is not practical since the hardware design is very complicated and the circuit dimension will be too large. Therefore, almost all conventional 2-D DCT/IDCT circuits, such as that disclosed in U.S. Pat. Nos. 4,791,598 and 5,249,146, utilize the structure having two 1-D processors connected in series.
FIG. 1 (Prior Art) depicts a 2-D DCT/IDCT circuit consisting of two 1-D processors. The DCT/IDCT circuit of FIG. 1 (Prior Art) performs two successive 1-D DCT/IDCT processes to achieve a 2-D transformation. The circuit includes a 1-D DCT/IDCT processor 15, a transpose buffer 16, another 1-D DCT/IDCT processor 17 and another transpose buffer 18. Two 1-D DCT/IDCT processes of a matrix X and its transpose matrix Z are carried out in 1-D DCT/IDCT processors 15 and 17 respectively. In order to keep the output data in correct order, two transpose buffers 16 and 18 are provided to interchange column elements and row elements of the matrices. There are two similar process stages in the circuit of FIG. 1 (Prior Art). That is, the function of a first stage consisting of 1-D DCT/IDCT processor 15 and transpose buffer 16 is similar to that of a second stage consisting of 1-D DCT/IDCT processor 17 and transpose buffer 18. Therefore, a minimal circuit dimension can be obtained by establishing a feedback loop from transpose buffer 16 to 1-D DCT/IDCT processor 15 and skipping elements of the second stage, i.e., 1-D DCT/IDCT processor 17 and transpose buffer 18.
Because the above-mentioned circuit has two operating stages, the executing time will be too long to carry out a real time operation. That is, even though the circuit dimension can be reduced, the circuit shown in FIG. 1 can not satisfy the high speed requirements of video systems.